Mechanikal Applications of the Harmless Error Rule in Cases of Prosecutorial Grand Jury Misconduct

Even though time-interleaved analog-to-digital converters (ADCs) help to achieve higher bandwidth with simpler individual ADCs, gain, offset, and time-skew mismatch between the channels degrade the achievable resolution. Of particular interest is the time-skew error between channels which results in nonuniform samples and thereby introducing distortion tones at the output of the time-interleaved ADC. Time-varying digital reconstructors can be used to correct the time-skew errors between the channels in a time-interleaved ADC. However, the complexity of such reconstructors increases as their bandwidth approaches the Nyquist band. In addition to this, the reconstructor needs to be redesigned online every time the time-skew error varies. Design methods that result in minimum reconstructor order require expensive online redesign while those methods that simplify online redesign result in higher reconstructor complexity. This paper proposes a technique that can be used to simplify the online redesign and achieve a low complexity reconstructor at the same time

Special Considerations in Estate Planning for Same-Sex and Unmarried Couples

Sub-Nyquist sampling makes use of sparsities in analog signals to sample them at a rate lower than the Nyquist rate. The reduction in sampling rate, however, comes at the cost of additional digital signal processing (DSP) which is required to reconstruct the uniformly sampled sequence at the output of the sub-Nyquist sampling analog-to-digital converter. At present, this additional processing is computationally intensive and time consuming and offsets the gains obtained from the reduced sampling rate. This paper focuses on sparse multi-band signals where the user band locations can change from time to time and the reconstructor requires real-time redesign. We propose a technique that can reduce the computational complexity of the reconstructor. At the same time, the proposed scheme simplifies the online reconfigurability of the reconstructor

Signal Reconstruction Algorithms for Time-Interleaved ADCs

An analog-to-digital converter (ADC) is a key component in many electronic systems. It is used to convert analog signals to the equivalent digital form. The conversion involves sampling which is the process of converting a continuous-time signal to a sequence of discrete-time samples, and quantization in which each sampled value is represented using a finite number of bits. The sampling rate and the effective resolution (number of bits) are two key ADC performance metrics. Today, ADCs form a major bottleneck in many applications like communication systems since it is difficult to simultaneously achieve high sampling rate and high resolution. Among the various ADC architectures, the time-interleaved analog-to-digital converter (TI-ADC) has emerged as a popular choice for achieving very high sampling rates and resolutions. At the principle level, by interleaving the outputs of M identical channel ADCs, a TI-ADC could achieve the same resolution as that of a channel ADC but with M times higher bandwidth. However, in practice, mismatches between the channel ADCs result in a nonuniformly sampled signal at the output of a TI-ADC which reduces the achievable resolution. Often, in TIADC implementations, digital reconstructors are used to recover the uniform-grid samples from the nonuniformly sampled signal at the output of the TI-ADC. Since such reconstructors operate at the TI-ADC output rate, reducing the number of computations required per corrected output sample helps to reduce the power consumed by the TI-ADC. Also, as the mismatch parameters change occasionally, the reconstructor should support online reconfiguration with minimal or no redesign. Further, it is advantageous to have reconstruction schemes that require fewer coefficient updates during reconfiguration. In this thesis, we focus on reducing the design and implementation complexities of nonrecursive finite-length impulse response (FIR) reconstructors. We propose efficient reconstruction schemes for three classes of nonuniformly sampled signals that can occur at the output of TI-ADCs. Firstly, we consider a class of nonuniformly sampled signals that occur as a result of static timing mismatch errors or due to channel mismatches in TI-ADCs. For this type of nonuniformly sampled signals, we propose three reconstructors which utilize a two-rate approach to derive the corresponding single-rate structure. The two-rate based reconstructors move part of the complexity to a symmetric filter and also simplifies the reconstruction problem. The complexity reduction stems from the fact that half of the impulse response coefficients of the symmetric filter are equal to zero and that, compared to the original reconstruction problem, the simplified problem requires only a simpler reconstructor. Next, we consider the class of nonuniformly sampled signals that occur when a TI-ADC is used for sub-Nyquist cyclic nonuniform sampling (CNUS) of sparse multi-band signals. Sub-Nyquist sampling utilizes the sparsities in the analog signal to sample the signal at a lower rate. However, the reduced sampling rate comes at the cost of additional digital signal processing that is needed to reconstruct the uniform-grid sequence from the sub-Nyquist sampled sequence obtained via CNUS. The existing reconstruction scheme is computationally intensive and time consuming and offsets the gains obtained from the reduced sampling rate. Also, in applications where the band locations of the sparse multi-band signal can change from time to time, the reconstructor should support online reconfigurability. Here, we propose a reconstruction scheme that reduces the computational complexity of the reconstructor and at the same time, simplifies the online reconfigurability of the reconstructor. Finally, we consider a class of nonuniformly sampled signals which occur at the output of TI-ADCs that use some of the input sampling instants for sampling a known calibration signal. The samples corresponding to the calibration signal are used for estimating the channel mismatch parameters. In such TI-ADCs, nonuniform sampling is due to the mismatches between the channel ADCs and due to the missing input samples corresponding to the sampling instants reserved for the calibration signal. We propose three reconstruction schemes for such nonuniformly sampled signals and show using design examples that, compared to a previous solution, the proposed schemes require substantially lower computational complexity

Prefilter-Based Reconfigurable Reconstructor for Time-Interleaved ADCs With Missing Samples

This brief proposes a reconstruction scheme for the compensation of frequency-response mismatch errors at the output of a time-interleaved analog-to-digital converter (TI-ADC) with missing samples. The missing samples are due to sampling instants reserved for estimating the channel mismatch errors in the TI-ADC. Compared with previous solutions, the proposed scheme offers substantially lower computational complexity

Efficient signal reconstruction scheme for time-interleaved ADCs

Time-interleaved analog-to-digital converters (ADCs) exhibit offset, gain, and time-skew errors due to channel mismatches. The time skews give rise to a nonuniformly sampled signal instead of the desired uniformly sampled signal. This introduces the need for a digital signal reconstructor that takes the "nonuniform samples" and generates the "uniform samples". In the general case, the time skews are frequency dependent, in which case a generalization of nonuniform sampling applies. When the bandwidth of a digital reconstructor approaches the whole Nyquist band, the computational complexity may become prohibitive. This paper introduces a new scheme with reduced complexity. The idea stems from recent multirate-based efficient realizations of linear and time-invariant systems. However, a time-interleaved ADC (without correction) is a time-varying system which means that these multirate-based techniques cannot be used straightforwardly but need to be appropriately analyzed and extended for this context

Efficient reconfigurable scheme for the recovery of sub-Nyquist sampled sparse multi-band signals

Sub-Nyquist sampling makes use of sparsities in analog signals to sample them at a rate lower than the Nyquist rate. The reduction in sampling rate, however, comes at the cost of additional digital signal processing (DSP) which is required to reconstruct the uniformly sampled sequence at the output of the sub-Nyquist sampling analog-to-digital converter. At present, this additional processing is computationally intensive and time consuming and offsets the gains obtained from the reduced sampling rate. This paper focuses on sparse multi-band signals where the user band locations can change from time to time and the reconstructor requires real-time redesign. We propose a technique that can reduce the computational complexity of the reconstructor. At the same time, the proposed scheme simplifies the online reconfigurability of the reconstructor

Правовая охрана интересов автомобильного перевозчика груза

Материалы III Междунар. науч. конф. студентов, аспирантов и молодых ученых, Гомель, 20 мая 2010 г

Efficient signal reconstruction scheme for time-interleaved ADCs

Time-interleaved analog-to-digital converters (ADCs) exhibit offset, gain, and time-skew errors due to channel mismatches. The time skews give rise to a nonuniformly sampled signal instead of the desired uniformly sampled signal. This introduces the need for a digital signal reconstructor that takes the "nonuniform samples" and generates the "uniform samples". In the general case, the time skews are frequency dependent, in which case a generalization of nonuniform sampling applies. When the bandwidth of a digital reconstructor approaches the whole Nyquist band, the computational complexity may become prohibitive. This paper introduces a new scheme with reduced complexity. The idea stems from recent multirate-based efficient realizations of linear and time-invariant systems. However, a time-interleaved ADC (without correction) is a time-varying system which means that these multirate-based techniques cannot be used straightforwardly but need to be appropriately analyzed and extended for this context

A Study on the Design of Reconfigurable ADCs

Analog-to-Digital Converters (ADCs) can be classified into two categories namely Nyquist-rate ADCs and OversampledADCs. Nyquist-rate ADCs can process very high bandwidths while Oversampling ADCs provide high resolution using coarse quantizers and support lower input signal bandwidths. This work describes a Reconfigurable ADC (R-ADC) architecture which models 14 different ADCs utilizing four four-bit flash ADCs and four Reconfigurable Blocks (RBs). Both Nyquist-rate and Oversampled ADCs are included in the reconfiguration scheme. The R-ADC supports first- and second-order Sigma-Delta (ΣΔ) ADCs. Cascaded ΣΔ ADCs which provide high resolution while avoiding the stability issues related to higher order ΣΔ loops are also included. Among the Nyquist-rate ADCs, pipelined and time interleaved ADCs are modeled. A four-bit flash ADC with calibration is used as the basic building block for all ADC configurations. The R-ADC needs to support very high sampling rates (1 GHz to 2 GHz). Hence switched-capacitor (SC) based circuits are used for realizing the loop filters in the ΣΔ ADCs. The pipelined ADCs also utilize an SC based block called Multiplying Digital-to-Analog Converter (MDAC). By analyzing the similarities in structure and function of the loop filter and MDAC, a RB has been designed which can accomplish the function of either block based on the selected configuration. Utilizing the same block for various configurations reduces power and area requirements for the R-ADC. In SC based circuits, the minimum sampling capacitance is limited by the thermal noise that can be tolerated in order to achieve a specific ENOB. The thermal noise in a ΣΔ ADC is subjected to noise shaping. This results in reduced thermal noise levels at the inputs of successive loop filters in cascaded or multi-order ΣΔ ADCs. This property can be used to reduce the sampling capacitance of successive stages in cascaded and multi-order ΣΔ ADCs. In pipelined ADCs, the thermal noise in successive stages are reduced due to the inter-stage gain of the MDAC in each stage. Hence scaling of sampling capacitors can be applied along the pipeline stages. The RB utilizes the scaling of capacitor values afforded by the noise shaping property of ΣΔ loops and the inter-stage gain of stages in pipelined ADCs to reduce the total capacitance requirement for the specified Effective Number Of Bits (ENOB). The critical component of the RB is the operational amplifier (opamp). The speed of operation and ENOB for different configurations are determined by the 3 dB frequency and DC gain of the opamp. In order to find the specifications of the opamp, the errors introduced in ΣΔ and pipelined ADCs by the finite gain and bandwidth of the opamp were modeled in Matlab.The gain and bandwidth requirements for the opamp were derived from the simulation results. Unlike Nyquist-rate ADCs, the ΣΔ ADCs suffer from stability issues when the input exceeds a certain level. The maximum usable input level is determined by the resolution of the quantizer and the order of the loop filter in the ΣΔADC. Using Matlab models, the maximum value of input for different oversampling ADC configurations in the R-ADC were found. The results obtained from simulation are comparable to the theoretical values. The cascaded ADCs require digital filter functions which enable the cancellation of quantization noise from certain stages. These functions were implemented in Matlab. For the R-ADC, these filter functions need to run at very high sampling rates. The ΣΔ loop filter transfer functions were chosen such that their coefficients are powers of two, which would allow them to be implemented as shift and add operations instead of multiplications. The R-ADC configurations were simulated in Matlab. A schematic for the R-ADC was developed in Cadence using ideal switches and a finite gain, single-pole operational transconductance amplifier model. The ADC configuration was selected by four external bits. Performance parameters such as SNR, SNDR and SFDR obtained from simulations in Cadence agree with those from Matlab for all ADC configurations